How to Install and Uninstall perl-Verilog-CodeGen.noarch Package on Fedora 34
Last updated: November 16,2024
1. Install "perl-Verilog-CodeGen.noarch" package
Please follow the instructions below to install perl-Verilog-CodeGen.noarch on Fedora 34
$
sudo dnf update
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$
sudo dnf install
perl-Verilog-CodeGen.noarch
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2. Uninstall "perl-Verilog-CodeGen.noarch" package
This is a short guide on how to uninstall perl-Verilog-CodeGen.noarch on Fedora 34:
$
sudo dnf remove
perl-Verilog-CodeGen.noarch
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$
sudo dnf autoremove
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3. Information about the perl-Verilog-CodeGen.noarch package on Fedora 34
Last metadata expiration check: 3:01:28 ago on Tue Sep 6 08:10:37 2022.
Available Packages
Name : perl-Verilog-CodeGen
Version : 0.9.4
Release : 35.fc34
Architecture : noarch
Size : 34 k
Source : perl-Verilog-CodeGen-0.9.4-35.fc34.src.rpm
Repository : fedora
Summary : Verilog code generator
URL : https://metacpan.org/release/Verilog-CodeGen
License : GPL+ or Artistic
Description : Provides an object-oriented environment to generate Verilog code for
: modules and testbenches. The Verilog::CodeGen module provides two
: functions, one to create a code template and another to create a Perl
: module which contains the device library. This module ,
: DeviceLibs::YourDesign, provides the class methods and contains the objects
: for every Verilog module; the objects are created based on a fixed
: template. The purpose of this module is to allow the generation of
: customized Verilog modules. A Verilog module can have a large number of
: parameters like input and output bus width, buffer depth, signal delay etc.
: The code generator allows to create an object that will generate the
: Verilog module code for arbitraty values of the parameters.
Available Packages
Name : perl-Verilog-CodeGen
Version : 0.9.4
Release : 35.fc34
Architecture : noarch
Size : 34 k
Source : perl-Verilog-CodeGen-0.9.4-35.fc34.src.rpm
Repository : fedora
Summary : Verilog code generator
URL : https://metacpan.org/release/Verilog-CodeGen
License : GPL+ or Artistic
Description : Provides an object-oriented environment to generate Verilog code for
: modules and testbenches. The Verilog::CodeGen module provides two
: functions, one to create a code template and another to create a Perl
: module which contains the device library. This module ,
: DeviceLibs::YourDesign, provides the class methods and contains the objects
: for every Verilog module; the objects are created based on a fixed
: template. The purpose of this module is to allow the generation of
: customized Verilog modules. A Verilog module can have a large number of
: parameters like input and output bus width, buffer depth, signal delay etc.
: The code generator allows to create an object that will generate the
: Verilog module code for arbitraty values of the parameters.