How to Install and Uninstall abc.x86_64 Package on Fedora 38
Last updated: May 20,2024
1. Install "abc.x86_64" package
This tutorial shows how to install abc.x86_64 on Fedora 38
$
sudo dnf update
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$
sudo dnf install
abc.x86_64
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2. Uninstall "abc.x86_64" package
This is a short guide on how to uninstall abc.x86_64 on Fedora 38:
$
sudo dnf remove
abc.x86_64
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$
sudo dnf autoremove
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3. Information about the abc.x86_64 package on Fedora 38
Last metadata expiration check: 2:37:29 ago on Sat Mar 16 22:59:57 2024.
Available Packages
Name : abc
Version : 1.01
Release : 40.git20230708.fc38
Architecture : x86_64
Size : 19 k
Source : abc-1.01-40.git20230708.fc38.src.rpm
Repository : updates
Summary : Sequential logic synthesis and formal verification
URL : https://people.eecs.berkeley.edu/~alanmi/abc/abc.htm
License : MIT-Modern-Variant AND MIT AND BSD-2-Clause AND BSD-3-Clause
Description : ABC is a growing software system for synthesis and verification of
: binary sequential logic circuits appearing in synchronous hardware
: designs. ABC combines scalable logic optimization based on And-Inverter
: Graphs (AIGs), optimal-delay DAG-based technology mapping for look-up
: tables and standard cells, and innovative algorithms for sequential
: synthesis and verification.
:
: ABC provides an experimental implementation of these algorithms and a
: programming environment for building similar applications. Future
: development will focus on improving the algorithms and making most of
: the packages stand-alone. This will allow the user to customize ABC for
: their needs as if it were a toolbox rather than a complete tool.
Available Packages
Name : abc
Version : 1.01
Release : 40.git20230708.fc38
Architecture : x86_64
Size : 19 k
Source : abc-1.01-40.git20230708.fc38.src.rpm
Repository : updates
Summary : Sequential logic synthesis and formal verification
URL : https://people.eecs.berkeley.edu/~alanmi/abc/abc.htm
License : MIT-Modern-Variant AND MIT AND BSD-2-Clause AND BSD-3-Clause
Description : ABC is a growing software system for synthesis and verification of
: binary sequential logic circuits appearing in synchronous hardware
: designs. ABC combines scalable logic optimization based on And-Inverter
: Graphs (AIGs), optimal-delay DAG-based technology mapping for look-up
: tables and standard cells, and innovative algorithms for sequential
: synthesis and verification.
:
: ABC provides an experimental implementation of these algorithms and a
: programming environment for building similar applications. Future
: development will focus on improving the algorithms and making most of
: the packages stand-alone. This will allow the user to customize ABC for
: their needs as if it were a toolbox rather than a complete tool.