How to Install and Uninstall iverilog Package on Kali Linux
Last updated: December 23,2024
1. Install "iverilog" package
This tutorial shows how to install iverilog on Kali Linux
$
sudo apt update
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$
sudo apt install
iverilog
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2. Uninstall "iverilog" package
Please follow the steps below to uninstall iverilog on Kali Linux:
$
sudo apt remove
iverilog
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$
sudo apt autoclean && sudo apt autoremove
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3. Information about the iverilog package on Kali Linux
Package: iverilog
Version: 12.0-2
Installed-Size: 6936
Maintainer: Debian Electronics Team
Architecture: amd64
Replaces: verilog (<< 10.2-1.1~)
Provides: verilog
Depends: libbz2-1.0, libc6 (>= 2.35), libgcc-s1 (>= 3.0), libreadline8 (>= 6.0), libstdc++6 (>= 11), zlib1g (>= 1:1.2.0)
Suggests: gtkwave
Breaks: verilog (<< 10.2-1.1~)
Size: 2035248
SHA256: 1e7b283d7eecacbcdd82dd420c8a32d4dc0cdce3afe4b95c425c77dc90599b63
SHA1: a9d1dd41bfd51e5c0b22251d0adc20ec72834454
MD5sum: 03d8700b54390edb8bd12239bbdafd6c
Description: Icarus verilog compiler
Icarus Verilog is intended to compile all of the Verilog HDL as
described in the IEEE-1364 standard. It is not quite there
yet. It does currently handle a mix of structural and behavioral
constructs.
.
The compiler can target either simulation, or netlist (EDIF).
Description-md5:
Homepage: http://iverilog.icarus.com
Tag: field::electronics, implemented-in::c++, interface::commandline,
role::program
Section: electronics
Priority: optional
Filename: pool/main/i/iverilog/iverilog_12.0-2_amd64.deb
Version: 12.0-2
Installed-Size: 6936
Maintainer: Debian Electronics Team
Architecture: amd64
Replaces: verilog (<< 10.2-1.1~)
Provides: verilog
Depends: libbz2-1.0, libc6 (>= 2.35), libgcc-s1 (>= 3.0), libreadline8 (>= 6.0), libstdc++6 (>= 11), zlib1g (>= 1:1.2.0)
Suggests: gtkwave
Breaks: verilog (<< 10.2-1.1~)
Size: 2035248
SHA256: 1e7b283d7eecacbcdd82dd420c8a32d4dc0cdce3afe4b95c425c77dc90599b63
SHA1: a9d1dd41bfd51e5c0b22251d0adc20ec72834454
MD5sum: 03d8700b54390edb8bd12239bbdafd6c
Description: Icarus verilog compiler
Icarus Verilog is intended to compile all of the Verilog HDL as
described in the IEEE-1364 standard. It is not quite there
yet. It does currently handle a mix of structural and behavioral
constructs.
.
The compiler can target either simulation, or netlist (EDIF).
Description-md5:
Homepage: http://iverilog.icarus.com
Tag: field::electronics, implemented-in::c++, interface::commandline,
role::program
Section: electronics
Priority: optional
Filename: pool/main/i/iverilog/iverilog_12.0-2_amd64.deb