How to Install and Uninstall yosys-abc Package on Kali Linux
Last updated: December 25,2024
1. Install "yosys-abc" package
Here is a brief guide to show you how to install yosys-abc on Kali Linux
$
sudo apt update
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$
sudo apt install
yosys-abc
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2. Uninstall "yosys-abc" package
Please follow the steps below to uninstall yosys-abc on Kali Linux:
$
sudo apt remove
yosys-abc
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$
sudo apt autoclean && sudo apt autoremove
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3. Information about the yosys-abc package on Kali Linux
Package: yosys-abc
Source: yosys
Version: 0.33-5
Installed-Size: 14691
Maintainer: Debian Science Maintainers
Architecture: amd64
Replaces: yosys (<< 0.32-1)
Depends: libbz2-1.0, libc6 (>= 2.34), libgcc-s1 (>= 3.3.1), libreadline8 (>= 6.0), libstdc++6 (>= 13.1), zlib1g (>= 1:1.1.4)
Breaks: yosys (<< 0.32-1)
Size: 5447412
SHA256: 1ecee1b676d7e3e7a024bcd62f2a833bc33168b36dcbbe15898d1eb29f2a2351
SHA1: 1c330f0c23c03259c33f70fe97cc056d364165a0
MD5sum: 2a87e8014a479409f6ccdc620ee470ea
Description: Sequential Logic Synthesis and Verification Algorithms
ABC is a system for synthesis and verification of binary sequential logic
circuits appearing in synchronous hardware designs. It combines scalable
logic optimization based on And-Inverter Graphs (AIGs), optimal-delay
DAG-based technology mapping for look-up tables and standard cells, and
innovative algorithms for sequential synthesis and verification.
.
This is a fork of berkeley-abc maintained by the YosysHQ team for use in
the yosys RTL synthesis framework.
Description-md5:
Homepage: https://github.com/YosysHQ/yosys
Section: electronics
Priority: optional
Filename: pool/main/y/yosys/yosys-abc_0.33-5_amd64.deb
Source: yosys
Version: 0.33-5
Installed-Size: 14691
Maintainer: Debian Science Maintainers
Architecture: amd64
Replaces: yosys (<< 0.32-1)
Depends: libbz2-1.0, libc6 (>= 2.34), libgcc-s1 (>= 3.3.1), libreadline8 (>= 6.0), libstdc++6 (>= 13.1), zlib1g (>= 1:1.1.4)
Breaks: yosys (<< 0.32-1)
Size: 5447412
SHA256: 1ecee1b676d7e3e7a024bcd62f2a833bc33168b36dcbbe15898d1eb29f2a2351
SHA1: 1c330f0c23c03259c33f70fe97cc056d364165a0
MD5sum: 2a87e8014a479409f6ccdc620ee470ea
Description: Sequential Logic Synthesis and Verification Algorithms
ABC is a system for synthesis and verification of binary sequential logic
circuits appearing in synchronous hardware designs. It combines scalable
logic optimization based on And-Inverter Graphs (AIGs), optimal-delay
DAG-based technology mapping for look-up tables and standard cells, and
innovative algorithms for sequential synthesis and verification.
.
This is a fork of berkeley-abc maintained by the YosysHQ team for use in
the yosys RTL synthesis framework.
Description-md5:
Homepage: https://github.com/YosysHQ/yosys
Section: electronics
Priority: optional
Filename: pool/main/y/yosys/yosys-abc_0.33-5_amd64.deb