How to Install and Uninstall verilator Package on Ubuntu 20.10 (Groovy Gorilla)
Last updated: December 22,2024
1. Install "verilator" package
Learn how to install verilator on Ubuntu 20.10 (Groovy Gorilla)
$
sudo apt update
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$
sudo apt install
verilator
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2. Uninstall "verilator" package
Please follow the instructions below to uninstall verilator on Ubuntu 20.10 (Groovy Gorilla):
$
sudo apt remove
verilator
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$
sudo apt autoclean && sudo apt autoremove
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3. Information about the verilator package on Ubuntu 20.10 (Groovy Gorilla)
Package: verilator
Architecture: amd64
Version: 4.038-1
Priority: optional
Section: universe/electronics
Origin: Ubuntu
Maintainer: Ubuntu Developers
Original-Maintainer: Debian Electronics Team
Bugs: https://bugs.launchpad.net/ubuntu/+filebug
Installed-Size: 20627
Depends: libc6 (>= 2.29)
Recommends: libsystemc-dev
Suggests: gtkwave
Filename: pool/universe/v/verilator/verilator_4.038-1_amd64.deb
Size: 4732076
MD5sum: 0ac90b7b44969b28737cc6a790fb38c2
SHA1: eb0cb3deb1801b7c3f7e9ff41824b14cbec42172
SHA256: 3ed130509d5493a3c95e7be97a00cfed7457b2aeb9c11eed96ea3a802c310836
SHA512: b3eaf481e4479c122eb5be3f880d7282f9fa5446e0c43b727a8ac53a63aa09394cd44adff71d39d9bec70beb98c42a5356b94fbc0542e2926c49e9ff4150748f
Homepage: http://www.veripool.org/wiki/verilator
Description-en: fast free Verilog simulator
Verilator is the fastest free Verilog HDL simulator, and beats many commercial
simulators. It compiles synthesizable Verilog (not test-bench code!), plus
some PSL, SystemVerilog and Synthesis assertions into C++ or SystemC code.
It is designed for large projects where fast simulation performance is of
primary concern, and is especially well suited to generate executable models
of CPUs for embedded software design teams.
Description-md5: 648a4acbea03c032658027a1f55bb2a8
Architecture: amd64
Version: 4.038-1
Priority: optional
Section: universe/electronics
Origin: Ubuntu
Maintainer: Ubuntu Developers
Original-Maintainer: Debian Electronics Team
Bugs: https://bugs.launchpad.net/ubuntu/+filebug
Installed-Size: 20627
Depends: libc6 (>= 2.29)
Recommends: libsystemc-dev
Suggests: gtkwave
Filename: pool/universe/v/verilator/verilator_4.038-1_amd64.deb
Size: 4732076
MD5sum: 0ac90b7b44969b28737cc6a790fb38c2
SHA1: eb0cb3deb1801b7c3f7e9ff41824b14cbec42172
SHA256: 3ed130509d5493a3c95e7be97a00cfed7457b2aeb9c11eed96ea3a802c310836
SHA512: b3eaf481e4479c122eb5be3f880d7282f9fa5446e0c43b727a8ac53a63aa09394cd44adff71d39d9bec70beb98c42a5356b94fbc0542e2926c49e9ff4150748f
Homepage: http://www.veripool.org/wiki/verilator
Description-en: fast free Verilog simulator
Verilator is the fastest free Verilog HDL simulator, and beats many commercial
simulators. It compiles synthesizable Verilog (not test-bench code!), plus
some PSL, SystemVerilog and Synthesis assertions into C++ or SystemC code.
It is designed for large projects where fast simulation performance is of
primary concern, and is especially well suited to generate executable models
of CPUs for embedded software design teams.
Description-md5: 648a4acbea03c032658027a1f55bb2a8